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data sheet 1997-09-01 ics for consumer electronics megatext and megatext plus ics sda 5273 / sda 5275 sda 5273-2 / sda 5275-2
data classification maximum ratings maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. characteristics the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. operating range in the operating range the functions given in the circuit description are fulfilled. for detailed technical information about processing guidelines and quality assurance for ics, see our short form catalog. megatext a and megatext plus ics sda 5273 / sda 5275 sda 5273-2 / sda 5275-2 revision history: 1997-09-01 previous releases: 11.96 page subjects (changes since last revision) 20 now also covers sda 5275-2 and sda 5273-2 versions; reset/chip initialization update published by siemens ag, bereich halbleiter, marketing-kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1997. all rights reserved. as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in ger- many or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you - get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. edition 1997-09-01
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 3 1997-09-01 contents page 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3 diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 megatext is a registered trademark of siemens ag
megatext and megatext plus ics preliminary data cmos ic sda 5273 / 75 sda 5273-2 / 75-2 p-lcc-68-1 p-sdip-52-1 1 features l single chip teletext ic l analog cvbs-input with onchip clamping circuitry l slicer l supports level 1, 2.5 and 3.5 etsi teletext standard l stores up to 14 teletext pages on chip l stores up to 2048 teletext pages with external 16 m memory l sda 5275: full level 2.5 processing l analog rgb-output l 41 latin script languages l 12 10 character size l parallel display attributes l 64 from 4096 colors selectable l enhanced flash modes l dynamically redefinable character set (drcs, pcs) l pixel graphics l fullscreen display (64 32 or 80 24 character positions) l horizontal and vertical scrolling l graphic cursors l 4:3 and 16:9 display l multinorm display (50/60/100/120 hz) l risc-processor l firmware downloadable l i 2 c / 3 wire uart-interface (1 mbit/s) l independent clocks for acquisition and display l tools for greatly simplified software development l 24-kbyte on-chip reconfigurable dram l 44160-bit character rom l one external crystal for all standards type ordering code package sda 5273 / 75 p on request p-lcc-68-1 sda 5273 / 75 s on request p-sdip-52-1 sda 5273-2 / 75-2p on request p-lcc-68-1 sda 5273-2 / 75-2s on request p-sdip-52-1 sda 5273c / 73-2c p on request p-lcc-68-1 sda 5273c / 73-2c s on request p-sdip-52-1 semiconductor group 4 1997-09-01
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 5 1997-09-01 pin configuration (top view) uep04657 10 9 8 7 6 5 4 3 2 1 12 11 27 28 13 14 v dd tm gpo out hs vs/vcs i 15 16 17 18 19 20 36 35 34 33 32 31 30 29 40 39 38 37 cvbs i sda scl corq blan b g r rgb-gnd casq 3 d 2 d d0 d1 23 22 21 24 25 26 0 11 a 10 a 48 49 50 51 41 42 43 44 45 46 52 47 o i clk- tcsq/fld xin x 1 2 ntq cen 1 ss v a9 weq rasq v ssa 2 v ss2 v bb v ss3 v ss4 a a1 a2 a3 a4 a5 a6 a7 a8 a dd v 1 ssa v 2 dd v 3 dd v ref v 4 dd v res /n.c. p-sdip-52-1
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 6 1997-09-01 1.1 pin definitions and functions pin no. p-sdip-52-1 symbol function 1 clk-io system clock input/output 2 tcsq/fld composite sync output/ field output 3 vs/vcs vertical sync input/output 4 hs horizontal sync input/output 5 xout 20.5-mhz crystal oscillator output 6 xin 20.5-mhz crystal oscillator input 7 gpo general purpose output 8 tm testpin, leave open or connect to v ss 9 cvbs cvbs-video signal input 10 v dd1 + 5 v digital supply 11 v dda + 5 v analog supply 12 v ssa1 analog ground 13 v dd2 + 5 v digital supply 14 res chip reset 15 v dd3 + 5 v digital supply 16 v ref + 3 v reference voltage input 17 v dd4 + 5 v digital supply 18 a8 external dram-address 19 a7 external dram-address 20 a6 external dram-address 21 a5 external dram-address 22 a4 external dram-address 23 a3 external dram-address 24 a2 external dram-address 25 a1 external dram-address 26 a0 external dram-address 27 a9 external dram-address 28 a10 external dram-address 29 a11 external dram-address 30 rasq row address strobe (dram) 31 weq write enable (dram) 32 d1 external dram-data
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 7 1997-09-01 1.1 pin definitions and functions (contd) 1) depends on version. please refer to the respective delta specification. pin no. p-sdip-52-1 symbol function 33 d0 external dram-data 34 d2 external dram-data 35 d3 external dram-data 36 v ss4 0 v digital supply 37 casq column address strobe 38 v ss3 0 v digital supply 39 v bb substrate bias voltage n.c. 1) 40 v ss2 0 v digital supply 41 v ssa2 analog ground 42 rgb-gnd rgb-ground 43 v ss1 0 v digital supply 44 r analog red display output 45 g analog green display output 46 b analog blue display output 47 blan blanking signal open drain output 48 corq contrast reduction open drain output 49 scl bidirectional i 2 c bus clock port 50 sda bidirectional i 2 c bus data port 51 i 2 cen i 2 c bus enable 52 intq interrupt request output to ext. controller
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 8 1997-09-01 pin configuration (top view) uep05514 27 a7 a6 28 a5 29 a4 30 a3 31 a2 32 a1 33 a0 34 a9 35 a10 36 a11 37 rasq 38 weq 39 d1 40 d0 41 d2 42 43 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 24 25 26 cvbs 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 gpo xout vs/vcs i sda corq blan b casq n.c. n.c. v d3 n.c. n.c. res n.c. n.c. n.c. n.c. g v 2 cen v dda v dd3 v dd4 v ss1 ss3 ss4 hs r scl tm xin tcsq/fld clk-io intq rgb-gnd ssa2 v bb ss2 v v v dd1 ssa1 v v dd2 n.c. a8 23 ref v /n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. p-lcc-68-1
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 9 1997-09-01 1.2 pin definitions and functions pin no. p-lcc-68-1 symbol function 1 intq interrupt request output to ext. controller 2 clk-io system clock input/output 3 tcsq/fld composite sync output/ field output 4 vs/vcs vertical sync input/output 5 hs horizontal sync input/output 6 xout 20.5-mhz crystal oscillator output 7 xin 20.5-mhz crystal oscillator input 8 gpo general purpose output 9 tm testpin, leave open or connect v ss 10 cvbs cvbs-video signal input 11 v dd1 + 5 v digital supply 12 v dda + 5 v analog supply 13 v ssa1 analog ground 14 n.c. not connected 15 n.c. not connected 16 v dd2 + 5 v digital supply 17 res chip reset 18 n.c. not connected 19 n.c. not connected 20 n.c. not connected 21 v dd3 + 5 v digital supply 22 n.c. not connected 23 v ref + 3 v reference voltage input 24 n.c. not connected 25 v dd4 + 5 v digital supply 26 a8 external dram-address 27 a7 external dram-address 28 a6 external dram-address 29 a5 external dram-address 30 a4 external dram-address 31 a3 external dram-address 32 a2 external dram-address
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 10 1997-09-01 1.2 pin definitions and functions (contd) 1) depends on version. please refer to the respective delta specification. pin no. p-lcc-68-1 symbol function 33 a1 external dram-address 34 a0 external dram-address 35 a9 external dram-address 36 a10 external dram-address 37 a11 external dram-address 38 rasq row address strobe (dram) 39 weq write enable (dram) 40 d1 external dram-data 41 d0 external dram-data 42 d2 external dram-data 43 d3 external dram-data 44 v ss4 0 v digital supply 45 casq column address strobe 46 n.c. not connected 47 n.c. not connected 48 n.c. not connected 49 v ss3 0 v digital supply 50 n.c. not connected 51 n.c. not connected 52 n.c. not connected 53 n.c. not connected 54 n.c. not connected 55 v ss2 0 v digital supply 56 v bb substrate bias voltage n.c. 1) 57 n.c. not connected 58 v ssa2 analog ground 59 rgb-gnd rgb-ground 60 v ss1 0 v digital supply 61 r analog red display output 62 g analog green display output 63 b analog blue display output
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 11 1997-09-01 1.2 pin definitions and functions (contd) pin no. p-lcc-68-1 symbol function 64 blan blanking signal open drain output 65 corq contrast reduction open drain output 66 scl bidirectional i 2 c bus clock port 67 sda bidirectional i 2 c bus data port 68 i 2 cen i 2 c bus enable
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 12 1997-09-01 2 electrical characteristics absolute maximum ratings parameter symbol limit values unit test condition min. typ. max. supply voltage v dd 0 6.0 v ambient temperature t a 070 c storage temperature t stg C 20 125 c power consumption p tot 1.8 w electrostatic discharge 2000 v 100 pf, 1 k w hbm according to mil-standard 883 method 3015.7 characteristics t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. supply voltages v ddd 4.7 5.0 5.3 v v dda 4.7 5.0 5.3 v v ddd = v dda ! supply currents i ddd 200 ma 20 pf load per pin i dda 60 ma inputs tristate of outputs: i 2 cen, hs, vs, gpo, res, d0-d3 h-input voltage v ih 2.0 v ddd v l-input voltage v il C 1.0 0.8 v input capacitance c i 7pf input leakage current i l 10 m a v ih = 5.5 v input current res i ih 100 m a v ih = 5.5 v
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 13 1997-09-01 characteristics (contd) t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. outputs ttl-outputs: a0-a11, d0-d3, rasq, casq, weq, hs, vs, gpo, intq, tcsq h-output voltage v oh 2.4 v ddd vC i oh = 0.2 ma l-output voltage v ol 0 0.4 v i ol = 1.6 ma load capacitance c l 50 pf transition period t r , t f 15 ns open drain outputs: blan, corq sink current i ol 5 ma low level output l-output voltage v ol 0.4 v i ol = 2 ma h-output voltage v oh v ddd v blan = 1: display megatext rgb-outputs blan = 0; display other source corq = 1; switch contrast reduction off corq = 0; switch contrast reduction on sourcefollower output: cvbs at pin tcsq dc-offset to cvbs-input 1.2 v gain g 0.9 output current i o 0.9 ma cvbs = 1 v, tcsq = 0 v output impedance r o 200 w cvbs = 1 v edge response t r 1 m s 10 to 90 %, 1 vpp, c l = 50 pf sync timing: hs, vs, tcsq sync output waveforms pulse width hs t wh 2 m s pulse width vs t wh 1 line vcs-waveform see diagram 6a, b tcsq-waveform see diagram 6a, b
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 14 1997-09-01 characteristics (contd) t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. output timing: hs, vs, tcsq hold and delay time with respect to 24-mhz system clock output: delay time t od 20 ns see diagram 2 hold time t oh 0ns see diagram 2 hold and delay time with respect to 24-mhz external system clock input: delay time not specified hold time not specified input timing: hs, vs no synchronous input mode specified! clock input/output (see diagram 1) clock input h-input voltage v ih 2.0 v ddd v l-input voltage v il C 1.0 0.8 v input capacitance c i 7pf input leakage current i l 10 m a v ih = 5.5 v period t c 40 24-mhz clock t c 35 27-mhz clock transition time t cr , t cl 3ns symmetry ratio t ch /t c 0.43 0.57 clock output h-output voltage v oh 2.4 v ddd vC i oh = 0.2 ma l-output voltage v ol 0 0.4 v i ol = 1.6 ma load capacitance c l 50 pf period t c 41.7 ns 20.5-mhz crystal transition time t cr , t cf 5ns symmetry ratio t ch /t c 0.3 0.5 ns
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 15 1997-09-01 characteristics (contd) for modes with external clock megatext may only be operated in freerun mode as sync master. hs may not be used as an input in these cases. the rgb-output voltage is proportional to v ref . t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. rgb-outputs v ref = 3 v no resistive load rgb-gnd = 0 v pin capacitance c p 7v output voltage range 0 2.2 v rgb-amplitude 1.1 1.25 1.55 v r83: rgb-gain (4:0) = 1f h dc-offset voltage 0.7 0.8 1.0 v r83: rgb-levl (2:0) = 7 clamp level 0 v dac-resolution 4 bit diff. non-linearity C 0.5 0.5 lsb r83: rgb-gain (4:0) = 1f h rgb-levl (2:0) = 0 int. non-linearity C 0.5 0.5 lsb output tracking C 0.5 0.5 lsb output resistance r o 270 w 3-db bandwidth 10 mhz c l = 50 pf bus connection: sda, scl, i 2 cen (see diagram 4) inputs: sda, scl h-input voltage v ih 3.0 v ddd v l-input voltage v il C 1.0 1.5 v input capacitance c i 7pf input leakage current i l 10 m a v ih = 5.5 v v dd = 0 v 5.5 v 1 2 p r o c l -----------------------
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 16 1997-09-01 characteristics (contd) t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. open drain outputs: sda, scl l-output voltage v ol 0 0.4 v i ol = 3 ma sink current i ol 10 ma i 2 c-mode timing megatext is an i 2 c-slave transmitter/receiver. the siemens i 2 c bus specification applies. scl-frequency f scl 0 100 khz i 2 cen = high transition time t r , t f 2 m s bus capacitance c bus 400 pf bus free before start t buf 4.7 m s hold time start t hsta 4.0 m s l-time clock t low 4.0 m s h-time clock t high 4.0 m s set-up time start t susta 4.0 m s hold time sda t hddat 0 m s set-up time sda t sudat 250 ns set-up time sda at stop t susto 4.0 m s output fall time t fo 0.2 m s 3 v to 1 v m3l-mode timing the megatext m3l-bus is specified in accordance with the standard usart-interface of micro controller sda 30c162. scl-frequency f scl 0 1.0 mhz 20.48-mhz crystal l-time clock t l 400 ns h-time clock t h 400 ns scl-load capacitance c scl 200 pf set-up time sda-input to scl-falling edge t dsl 100 ns hold time sda-input from scl-falling edge t dhh 400 ns
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 17 1997-09-01 characteristics (contd) t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. m3l-mode timing (contd) set-up time sda to i 2 cen- rising edge t im 400 ns set up time i 2 cen to sda- falling edge t is 400 ns i 2 cen-high time t ih 1000 ns delay from scl-falling edge until sda-open drain output stage changes impedance t do 400 600 ns l-sda level output impedance 100 w the resulting delay of sda-output data is the sum of the open drain stage plus the time determined by the bus capacitance and the external pullup resistor or the impedance of the internal open drain pulldown transistor respectively. wait condition i 2 cen = 0 to force the m3l-master to interrupt the transmission sequence until megatext is ready for more data, megatext can force down scl after the transmission of a complete byte. at that time the bus master has to switch its scl-output to high impedance and check the state of scl afterwards.during scl check i 2 cen has to be low. delay from scl-rising edge to scl forced low for wait- condition t dwait 500 750 ns an internal pullup transistor restores scl high level at the end of the wait-condition. scl-pullup time at the end of wait t rwait 70 100 ns reference voltage: v ref voltage level v ref 2.8 3.0 3.5 v input leakage current i l C 10 10 m a v ref = 3 v v ref influences the dac-range, the cvbs-output at pin tcsq and the cvbs-adc range.
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 18 1997-09-01 characteristics (contd) the center frequency of the megatext horizontal pll is proportional to the crystal frequency. in pal-mode the centre frequency is 15.625 khz for the typical crystal frequency of 20.48 mhz. deviations from the typical crystal frequency will shift the range of the horizontal frequencies where the pll is able to lock. t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. cvbs-input and adc ( v ref = 3 v) input leakage current i l C 1.0 1.0 m a cvbs = 2 v input capacitance c p 45 pf ext. coupling capacitance c cpl 100 nf sensitivity of clamp level to current leakage/injection C 15 15 mv/ m a i l = 2 m a c cpl = 100 nf adc-range 1.7 2.0 v v ref = 3 v cvbs-sync amplitude 0.1 v crystal oscillator: xin, xout bias resistance between xin, xout r xbias 60 120 180 k w small signal voltage gain g v 8 13 100 khz, 50 mvpp feedback capacitance c fb 4.0 pf pin capacitance c p 7.0 pf crystal nominal frequency f o 20.48 mhz effect of temperature and accuracy of adjustment d f/f o C 5 % + 5 % temperature range t a 070 c resonant impedance z r 40 w equivalent parallel cc l 15 pf crystal load 0.1 mw ext. capacitors c 1,2 15 pf
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 19 1997-09-01 characteristics (contd) t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. dram-interface (see diagram 5) the external dram is operated in page mode. the timing of the dram-interface signals are specified below. cycle time t wc 420 500 550 ns address hold time from ras t rah 25 ns address hold time from cas t cah 60 ns address set-up time from ras t asr 5ns address set-up time from cas t asc 5ns l-time ras t rasp 280 ns l-time cas t casl 70 ns h-time ras t rp 140 ns h-time cas t cp 70 ns refresh period 20 ms write cycle l-time we t wel 210 ns data set-up time to cas t ds 100 ns we set-up time to cas t rcs 0ns data hold time from cas t dh 55 ns data hold time from we t ohz 10 ns read cycle h-time we (output enable) t oel 210 ns access time from cas t cac 60 ns data hold time of dram t off 40 ns
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 20 1997-09-01 characteristics (contd) t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. reset/chip initialization a power-on reset or a reset pulse at pin res lead to a hardware reset and a software initialization of registers and internal dram. during initialization bus transfers are not allowed. at / after power-on a reset pulse at pin res is necessary. res may return to 0 after the supply voltage reached its lower limit for chip function (4.7 v). this may be achieved by a capacitor c between res and v dd and by a resistor r between res and v ss . the dimensions of r and c depend on the worst case rise time of v dd . initialization time after power- on or falling edge of res t init 25 ms v dd greater 4.7 v if the supply voltage drops below v dd min , the ic has to be reset by pin res. pulse width res 100 ns high level at pin res causes chip reset. in rare cases, the ic may remain in a permanent reset state after power up, depending on the applicational context. after power up, the software should check proper operation. in case the megatext does not react properly, power supply should be switched off for at least 3 s. after that, power supply can be switched on again. other items horizontal frequency pull-in range of cvbs-pll: 15 15.625 16.2 khz pal 20.48 mhz crystal 15.2 15.748 16.3 khz ntsc 20.48 mhz crystal horizontal frequency pull-in range of display-pll: 15 15.625 16.2 khz 20.48 mhz crystal
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 21 1997-09-01 3 diagrams timing diagram 1 timing diagram 2 uet04660 t cr t cf t ch t cl t c clk 2.0 v 1.5 v 0.8 v uet04662 od t 2.4 v 1.5 v 0.8 v 2.4 v 0.8 v vs hs t oh oh t t od w t clk_out
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 22 1997-09-01 timing diagram 3a i 2 c-bus mode uet04815 scl sda cen i 2 t buf t high t low f t v il ih v v il ih v v il ih v buf t t susta sudat t t hddat susto t
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 23 1997-09-01 timing diagram 3b m3l-bus mode uet04816 scl is t sda cen i 2 scl wait condition t buf t high t low f tt r t im ds t dhh tt dhh dsl t t do wait t dwait rwait t v ih il v v ol ol v v il ih v v il ih v v il ih v buf t
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 24 1997-09-01 timing diagram 4a dram-page mode write cycle data from sda 527x column address t rasq casq t cp asr t asc t t casl d3 d0... weq a11 a0... row address t rp t we t rah ds t t rasp cah t cp casl t uet04663 ohz column address dh t wel t wc t data from sda 527x ds t t dh t
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 25 1997-09-01 timing diagram 4b dram-page mode read cycle data from ram column address cah rah casq rasq t t asb cp asc t t casl t weq d3 d0... a11 a0... row address t rp t oe t t cac t rasp t cp casl t uet04664 column address t t off oel rc t data from ram cac t t off
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 26 1997-09-01 timing diagram 5a vcs and tcs in pal freerun mode ued04865 a) b) c) 04.7 0 2.35 0 32 34.35 27.3 32 64 64 59.3 64 t [ m s] ] s m [ t ] s m [ t 622 623 624 625 1 2 3 4 5 6 310 311 312 313 314 315 316 317 318 319 (309) (310) (311) (312) 12345 6 (6) (5) (4) (3) (2) (1) 309 310 311 312 1 2 3 4 5 6 (1) (2) (3) (4) (5) (6) (311) (312) (313) (310) (621) (624) (623) (622) (624) (625) (626) (623) vcs vcs tcs tcs tcs interlaced interlaced non- interlaced -312/312 lines -313/312 lines -626/624 lines main pulse equalizing pulse line sync pulse timing with tolerances 100 ns (312) (311) (310) (309) 6 5 4 3 2 1 625 624 623 622 319 318 317 316 315 314 313 312 311 310
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 27 1997-09-01 timing diagram 5b vcs and tcs in ntsc freerun mode interlaced interlaced non- interlaced -262/262 lines -263/262 lines -526/524 lines tcs tcs tcs vcs vcs 0 4.7 63.6 63.6 31.8 27.1 0 34.1 2.3 63.6 0 main pulse equalizing pulse line sync pulse ued04872 58.9 31.8 522 (259) 523 (260) 524 (261) 525 (262) 1 2 3 4 5 6 t [ s] t [ s] t [ s] 260 261 262 263 264 (1) 265 (2) 266 (3) 267 (4) 268 (5) 269 (6) 259 (260) (521) (523) 260 (261) (522) (524) 261 (262) (523) (525) 262 (263) (524) (526) 1 (1) 2 (2) 3 (3) 4 (4) 5 (5) 6 (6) 522 (259) 523 (260) 524 (261) 525 (262) 1 2 3 4 5 6 260 261 262 263 264 (1) 265 (2) 266 (3) 267 (4) 268 (5) 269 (6) a) b) c) m m m
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 28 1997-09-01 application circuit ues04659 rasq weq 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 cvbs 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 gpo xout vs i sda scl corq blan b v reset g v 2 cen v v ss1 ssa2 ss4 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 sda 527x 10 nf 220 v dd zd v 3 220 nf nf 100 dd v v ss 4.7 k w w 150 150 w w k 4.7 v dd blank reduction dd v 22 pf hs hs intq scl g b ttl vs ttl cvbs cen 2 i 270 w 1.15 vpp v dd 10 m f 470 w ref. v 5 2 vpp 20.48 mhz xin tm tcsq clk intq r tcsq ttl r sda contrast w k 100 rgb-gnd bb v ss2 v n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. casq dram a1 a0 a9 a10 a11 d1 d0 d2 d3 a2 a3 a4 a5 a6 a7 dd4 v dd1 v dda v ssa1 v dd2 v dd3 v ref n.c. n.c. n.c. n.c. n.c. n.c. n.c. a8 k w 220 f n ss3 v 22 pf
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 29 1997-09-01 4 package outlines gpl05099 0.81 max 1.27 0.43 0.1 0.18 m 68x d a-b 20.32 0.1 5.08 max 3.5 0.2 0.5 min 0.2 1.2 x 45? 23.3 0.3 24.21 0.07 25.28 -0.26 1) 0.38 m d a-b 34x a b d 1 68 0.5 x 45? 3 x 24.21 0.07 1) 25.28 -0.26 1.1 x 45? index marking 1) does not include plastic or metal protrusions of 0.15 max per side p-lcc-68-1 (smd) (plastic leaded chip carrier) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
sda 5273 / 75 sda 5273-2 / 75-2 semiconductor group 30 1997-09-01 46.1 0.25 14.02 15.24 1.78 0.46 52 27 126 1.3 max 0.5 min 3.43 4.83 max -0.3 0.25 -0.4 0.05 0.1 0.25 max +1.7 index marking +0.7 15.24 m 0.25 52x plastic package, p-sdip-52-1 (plastic dual in-line package) gpd05262 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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